In recent years, reduction in weight and size of devices that have a built-in computer, systems such as a personal computer, television receiver and, VTR, is being advanced. For this reason, integration in which various kinds of functions are incorporated in the computer is being executed. Namely, reduction in weight and size as a system is accomplished by constructing at least part of the circuits, which have been provided outside the microcomputer conventionally constructed as one chip, for realizing various kinds of functions on the one chip. For this purpose, such a microcomputer equipped is proposed that has a region which is a so-called "Sea of gate (SOG) region" definable by the user is proposed. The SOG region is generally constituted of a gate array, a master slice or a programmable logic array (PLA). By constructing a part of the circuits necessary for the system required by the user in the SOG region, it becomes possible to reduce the number of circuits provided outside the one-chip microcomputer.
Referring to FIG. 1, such a microcomputer 101 is constituted as an integrated circuit, and consists of a central processing unit (CPU) 102 which executes programs, and an SOG region 103 which receives the signal from CPU via an external terminal 1011 and carries out processing based on the signal. The central processing unit 102 is connected to the SOG region 103 via signal lines 1021, 1022 and 1023. The SOG region 103 is connected to the external terminal 1011 provided outside the one-chip microcomputer 101 via a signal line 1031. A peripheral device 104 is connected to the external terminal 1011 via a signal line 1041.
The CPU 102 executes the program and outputs an instruction to the SOG region. In response to the instruction received from CPU 102, the SOG region 103 outputs a signal and data that control the peripheral device 104 to the peripheral device 104 via the external terminal 1011. The peripheral device executes processing based on the received signal and the data. Here, the case of the peripheral device 104 is a printer will be described as an example. In this case, CPU 102 outputs a printing instruction to the SOG region 103. The SOG region 103 that received the instruction outputs a control signal and data to the external terminal 1011. The printer 104 that received the control signal and the data executes printing based on the received control signal and the data.
When the SOG region 103 is incorporated in the microcomputer 101, the user can carry out design of a circuit in the interior of the SOG region 103 in order to obtain a system functions required. For example, in the above example the SOG region 103 functioning as a printer interface. Then, the user confirms the operation of the SOG region 103 with a completed circuit design by a simulation that uses a work station or the like. The system required by the user is completed when the microcomputer 101 with the finished design of the SOG region 103 is loaded. However, the debugging of the completed system is impossible until a sample of the completed product in which the completed circuit design of the SOG region 103 is incorporated in the computer 101. Accordingly, it is necessary to wait until a sample of the microcomputer with the completed circuit design of the SOG region 103 becomes available. Because of this, the time from design to completion of the microcomputer 101 is prolonged. Moreover, when defects are found by debugging in the SOG region 103 of the microcomputer 101 with completed circuit design of the SOG region 103, it becomes necessary to modify the circuit design and remake the SOG region 103. Therefore, the development cost of the microcomputer 101 will have to be increased.
Furthermore, the SOG region in the microcomputer 101 is required to receive a control signal and data from CPU which is used only within the microcomputer 101. In other words, the SOG region 103 receives an internal signal and data which are not output normally to outside the microcomputer 101. Accordingly, it is not possible to design a gate array with functions needed by the user outside the microcomputer 101, and to receive an instruction from CPU 102 at this gate array. Because of this, it is not possible to carry out debugging of the system by the use of this gate array. Therefore, it is not possible to deal with the design approach in which system debugging is carried out by installing a gate array designed by the user outside the microcomputer, and to incorporate the SOG region 103 into the microcomputer when there no problem is found in the gate array.
As described in the above, a system having a microcomputer 101 with a built-in SOG region 103 has a problem in that debugging is not possible until a completed sample with finished circuit design of the SOG region 103 becomes available.